PINSEL=00, PCLKS=0, TGL=0, PRE=000
Pulse Width Timer Control Register
| PRE | PWT Clock Prescaler (CLKPRE) Setting 0 (000): Clock divided by 1. 1 (001): Clock divided by 2. 2 (010): Clock divided by 4. 3 (011): Clock divided by 8. 4 (100): Clock divided by 16. 5 (101): Clock divided by 32. 6 (110): Clock divided by 64. 7 (111): Clock divided by 128. |
| LVL | PWTIN Level when Overflows |
| TGL | PWTIN states Toggled from last state 0 (0): The selected PWTIN hasn’t changed its original states from last time. 1 (1): The selected PWTIN has toggled its states. |
| PINSEL | PWT Pulse Inputs Selection 0 (00): PWTIN[0] is enabled. 1 (01): PWTIN[1] is enabled. 2 (10): PWTIN[2] enabled. 3 (11): PWTIN[3] enabled. |
| PCLKS | PWT Clock Source Selection 0 (0): BUS_CLK is selected as the clock source of PWT counter. 1 (1): Alternative clock is selected as the clock source of PWT counter. |